An Adiabatic Logic Implementation of a Reversible Cellular Automaton

Adiabatic circuit techniques have lately been a topic of interest in the low-power design community, but nobody has yet designed a complete computer using only adiabatic logic. We have (almost) completed the circuit design and layout of a simple fully-adiabatic processing element (PE) that nevertheless comprises a general-purpose parallel processor when tiled in large arrays. This PE implements the local update rule for Margolus's Billiard Ball Model Cellular Automaton 3], a reversible universal model of computation. The PE is implemented using Younis and Knight's SCRL logic family 1]. Our cell contains just 292 transistors and tiles on a 131 117 m 2 grid in the HP14 process. Hand-calculations indicate that our adiabatic circuit can operate with up to about 1000 times the energy eeciency of the equivalent standard CMOS circuit.